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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
= Target Spec =
AK4704
2ch 24bit DAC with AV SCART switch
GENERAL DESCRIPTION The AK4704 offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture for its modulator, the AK4704 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4704 integrates a combination of SCF and CTF filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. The AK4704 also including the audio switches, volumes, video switches, video filters, etc. designed primarily for digital set-top-box systems. The AK4704 is offered in a space saving 48-pin LQFP package. FEATURES DAC Sampling Rates Ranging from 8kHz to 50kHz 64dB High Attenuation 8x FIR Digital Filter 2nd order Analog LPF On chip Buffer with Single-ended Output Digital de-emphasis for 32k, 44.1k and 48kHz sampling I/F format: 24bit MSB justified, I2S, 18/16bit LSB justified Master clock: 256fs, 384fs High Tolerance to Clock Jitter Analog switches for SCART Audio section THD+N: -86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Stereo Analog Volume with Zero-cross Detection Circuit (+6dB to -60dB & Mute) Six Analog Inputs Two Stereo Input (TV&VCR SCART) One Stereo Input (changeover to internal DAC) Five Analog Outputs Two Stereo Outputs (TV, VCR SCART) One Mono Output (Modulator) Pop Noise Free Circuit for Power on/off Video section Integrated LPF: -40dB@27MHz 75ohm driver 6dB Gain for Outputs Adjustable gain Four CVBS/Y inputs (ENCx2, TV, VCR), Three CVBS/Y output (RF, TV, VCR) Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR) Bi-directional control for VCR-Chroma/Red Two G and B inputs (ENC, VCR), One G and B outputs (TV) Y/C Mixer for RF output VCR input monitor Loop-through Mode for standby Auto-Startup Mode for power saving SCART pin#16(Fast Blanking), pin#8(Slow Blanking) Control Power supply 5V+/-5% and 12V+/-5% Low Power Dissipation / Low Power Standby Mode Package Small 48pin LQFP
Rev. 0.5 -1-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
VD VP VSS -6dB/0dB/ +2.44/+4dB MCLK BICK LRCK SDTI Volume #0 TV1/0 VCRINL VCRINR Volume #1 MONO TVOUTL +6 to -60dB (2dB/step) VOL MONOOUT
DAC
TVOUTR
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) SCK SDA PDN Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="0")
VD VP VSS +6 to -60dB 0dB/+6dB (NC) DACL DACR (NC) Volume #2 TV1/0 VCRINL VCRINR Volume #1 MONO TVOUTR TVOUTL (2dB/step) VOL MONOOUT
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) SCK SDA PDN Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="1")
Rev. 0.5 -2-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
( Typical connection )
VVD1 VVD2 VVSS 6dB RFV
( Typical connection ) RF Mod
ENC CVBS/Y ENC Y VCR CVBS/Y TV CVBS
ENCV ENCY VCRVIN TVVIN 0, 1, 2, 3dB 6dB TVVOUT
ENC R/C ENC C VCR R/C
ENCRC ENCC VCRRC 6dB TVRC TV SCART
ENC G/CVBS VCR G
ENCG VCRG 6dB TVG
ENC B VCR B
ENCB VCRB Monitor 6dB TVB
FILT
6dB
VCRVOUT
VCR SCART
6dB VCRC
Video Block
( Typical connection ) VCR FB VCRFB 2V 0V 6dB TVFB
( Typical connection )
TV SCART
0/ 6/ 12V
TVSB
VCRSB 0/ 6/ 12V
VCR SCART
Monitor
INT
Video Blanking Block
Rev. 0.5 -3-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Ordering Guide
AK4704 -10 +70C 48pin LQFP (0.5mm pitch)
Pin Layout
VCRVOUT
MCLK
LRCK
TVFB
BICK
SDTI
PDN
SDA
RFV
SCL
VD 38
48
47
46
45
43
42
41
40
44
39
37 36 35 34 33 32
VSS
VCRC VVSS TVVOUT VVD2 TVRC TVG TVB VVD1 ENCB ENCG ENCRC ENCC
1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 19 20 21 14 17 18 22 23 24 Top View
PVCOM DVCOM VP MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR FILT TVINL TVINR VCRINL
31 30 29 28 27 26 25
VCRVIN
VCRSB
TVVIN
VCRG
ENCV
VCRB
Main difference between AK4702 and AK4704 Items Audio Audio bits Digital filter attenuation level +4dB gain at DAC volume#0 (total: +10dB max) DAC power-down/analog input mode Volume#1 output for VCROUTL/R switch matrix MONO mixing for VCROUTL/R MONO input Video Video filter 150ohm video driver for modulator Y/C mixer for modulator VCR video input monitor VCR Slow Blanking monitor in output mode. TV/VCR CVBS input detection & Power Save Mode Others I2C speed (max) Mask bits for INT function (09H)
INT
AK4702 AK4704 18bit 24bit 54dB 64dB X X X X X X X X X enabled disabled X 100kHz 400kHz X -: NOT available. X: Available
Rev. 0.5 -4-
VCRINR
VCRRC
VCRFB
ENCY
TVSB
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
PIN/FUNCTION
No. 1 2 3 4 Pin Name VCRC VVSS TVVOUT VVD2 I/O O O Function Chrominance Output Pin for VCR Video Ground Pin. 0V. Composite/Luminance Output Pin for TV Video Power Supply Pin #2. 5V. Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Red/Chrominance Output Pin for TV Green Output Pin for TV Blue Output Pin for TV Video Power Supply Pin #1. 5V. Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Blue Input Pin for Encoder Green Input Pin for Encoder Red/Chrominance Input Pin1 for Encoder Chrominance Input Pin2 for Encoder Composite/Luminance Input Pin1 for Encoder Composite/Luminance Input Pin2 for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance Input Pin for VCR Green Input Pin for VCR Blue Input Pin for VCR Interrupt Pin for Video Blanking Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin Filter Pin Normally connected to VVSS with a 0.1F ceramic capacitor. Rch Analog Output Pin1 Lch Analog Output Pin1 Rch Analog Output Pin2 Lch Analog Output Pin2 MONO Analog Output Pin Power Supply Pin. 12V. Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. DAC Common Voltage Pin Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Audio Common Voltage Pin Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. The caps affect the settling time of audio bias level.
5 6 7 8
TVRC TVG TVB VVD1
O O O -
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT VCRSB TVSB VCRINR VCRINL TVINR TVINL FILT VCROUTR VCROUTL TVOUTR TVOUTL MONOOUT VP
I I I I I I I I I I I I O I/O O I I I I O O O O O O -
35
DVCOM
O
36
PVCOM
O
Rev. 0.5 -5-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
PIN/FUNCTION (Continued)
Ground Pin. 0V. DAC Power Supply Pin. 5V. Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. 39 MCLK I Master Clock Input Pin at DAPD="0". (NC) NC (No Connection) pin at DAPD="1". 40 BICK I Audio Serial Data Clock Pin at DAPD="0". DACR Rch Analog Audio Input Pin at DAPD="1". 41 SDTI I Audio Serial Data Input Pin at DAPD="0". (NC) I NC (No Connection) pin at DAPD="1". 42 LRCK I L/R Clock Pin at DAPD="0". DACL I Lch Analog Audio Input Pin at DAPD="1". 43 SCL I Control Data Clock Pin 44 SDA I/O Control Data Pin 45 PDN I Power-Down Mode Pin When at "L", the AK4704 is in the power-down mode and is held in reset. The AK4704 should always be reset upon power-up. 46 RFV O Composite Output Pin for RF modulator 47 VCRVOUT O Composite/Luminance Output Pin for VCR 48 TVFB O Fast Blanking Output Pin for TV Note: All input pins should not be left floating. 37 38 VSS VD -
Rev. 0.5 -6-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Internal Equivalent Circuits
Pin No. 39 40 41 42 43 45 Pin Name MCLK BICK SDTI LRCK SCL PDN Type Equivalent Circuit VD (60k)
200
Description
Digital IN (DAPD="0") Analog IN (DAPD="1")
VSS
The 60kohm is attached only for BICK and LRCK.
VD 200
44
SDA
Digital I/O
I2C Bus voltage must not exceed VD.
VSS
VP
21
INT
Digital OUT
Normally connected to VD(5V) through 10kohm resistor externally.
VSS
46 47 48 1 3 5 6 7
RFV VCROUT TVFB VCRC TVVOUT TVRC TVG TVB
VVD1
VVD2
Video OUT
VVSS
VVSS
VP
VD 68k 200
28
FILT
Filter OUT
VSS
1k
Normally connected to VVSS (0V) through 0.1F capacitor externally.
VSS
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Pin No. 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
Type
Equivalent Circuit
VVD1 200
Description
Video IN
VVSS
VP 200
VP
22 23
VCRSB TVSB
Video SB
(120k) VSS VSS VP VSS
The 120kohm is not attached for TVSB.
24 25 26 27
VCRINR VCRINL TVINR TVINL
200
Audio IN
VSS VP VP 100
29 30 31 32 33
VCROUTR VCROUTL TVOUTR TVOUTL MONOOU T
Audio OUT
VSS
VSS
VD
VD 100
VD
35 36
DVCOM PVCOM
VCOM OUT
VSS VSS
VSS
Rev. 0.5 -8-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V;Note: 1) Parameter Power Supply Symbol VD VVD1 VVD2 VP |VSS-VVSS| (Note: 2) IIN VIND VINV VINA VINA Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 14 0.3 10 VD+0.3 VVD1+0.3 VP+0.3 VD+0.3 70 150 Units V V V V V mA V V V V C C
Input Current (any pins except for supplies) Input Voltage Video Input Voltage Audio Input Voltage (except DACL/R pins) Audio Input Voltage (DACL/R pins) Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. Note: 2. VSS and VVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=VVSS=0V; Note: 1) Parameter Power Supply Symbol VD VVD1=VVD2 VP Note: 3. Analog output voltage scales with the voltage of VD. AOUT (typ@0dB) = 2Vrms x VD/5. min 4.75 4.75 11.4 typ 5.0 5.0 12 max 5.25 5.25 12.6 Units V V V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs) Power Supplies Power Supply Current Normal Operation (PDN = "H"; Note: 4) TBD TBD VD TBD TBD VVD1+VVD2 TBD TBD VP Power-Down Mode (PDN = "L"; Note: 5) 100 10 VD 100 10 VVD1+VVD2 100 10 VP Note: 4. STBY bit ="L", All video outputs active. No signal, no load for A/V switches. fs=48kHz "0"data input for DAC. Note: 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS.
mA mA mA A A A
Rev. 0.5 -9-
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
DIGITAL CHARACTERISTICS (Ta = 25C; VD = 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA, INT pin: Iout= 1mA) Input Leakage Current Iin -
typ -
max 0.8 0.4 100
Units V V V A
ANALOG CHARACTERISTICS (AUDIO) (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz 20kHz; RL 4.5k; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2 Vrms Input Resistance 100 150 k Analog Input: (DACL/DACR pin) Analog Input Characteristics Input Voltage 1 Vrms Input Resistance TBD TBD k Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note: 6) Analog Output Characteristics Volume#0 Gain (DVOL1-0 = "00") 0 dB (DVOL1-0 = "01") -6 dB (DVOL1-0 = "10") +2.44 dB (DVOL1-0 = "11". Note: 7) +4 dB Volume#1 Step Width (+6dB to -12dB) 1.6 2 2.4 dB (-12dB to -40dB) 0.5 2 3.5 dB (-40dB to -60dB) 0.1 2 3.9 dB THD+N (at 2Vrms output. Note: 8) -86 -80 dB (at 3Vrms output. Note: 8, Note: 9) -60 dB Dynamic Range (-60dB Output, A-weighted. Note: 8) 92 96 dB S/N (A-weighted. Note: 8) 92 96 dB Interchannel Isolation (Note: 8, Note: 10) 80 90 dB Interchannel Gain Mismatch (Note: 8, Note: 10) 0.3 dB Gain Drift 200 ppm/C Load Resistance (AC-Lord; Note: 11) TVOUTL/R, VCROUTL/R, MONOOUT 4.5 k Output Voltage (Note: 11, Note: 12) 1.85 2 2.15 Vrms Power Supply Rejection (PSR. Note: 13) 50 dB Note: 6. Measured by Audio Precision System Two Cascade. Note: 7. Output clips over -2.5dBFS digital input. Note: 8. DAC to TVOUT Note: 9. Except VCROUTL/VCROUTL pins. Note: 10. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS. Note: 11. THD+N : -80dB(min. at 2Vrns), -60dB(typ. at 3Vrms). Note: 12. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD, Stereo output (typ@0dBFS) = 2Vrms x VD/5 when volume#0=volume#1=0dB. Do not output signals over 3Vrms. Note: 13. The PSR is applied to VD with 1kHz, 100mV.
Rev. 0.5 - 10 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
FILTER CHARACTERISTICS (Ta = 25C; VP=11.412.6V, VD = 4.755.25V, VVD1=VVD2 = 4.755.25V; fs = 48kHz; DEM0 = "1", DEM1 = "0") Parameter Symbol min typ max Units Digital filter PB 0 21.77 kHz Passband (Note: 14) 0.05dB 24.0 kHz -6.0dB Stopband (Note: 14) SB 26.23 kHz Passband Ripple PR dB 0.01 Stopband Attenuation SA 64 dB Group Delay (Note: 15) GD 24 1/fs Digital Filter + LPF FR dB Frequency Response 0 20.0kHz 0.5
Note: 14. The passband and stopband frequencies scale with fs (system sampling rate). e.g.) PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note: 15. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18/24bit data of both channels to input register to the output of analog signal.
Rev. 0.5 - 11 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
ANALOG CHARACTERISTICS (VIDEO) (Ta = 25C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= "00", YC="0" unless specified.) Parameter Conditions min typ Sync Tip Clamp Voltage at output pin. 0.7 Chrominance Bias Voltage at output pin. 2.2 Gain Input=0.3Vp-p, 100kHz 5.5 6 RGB Gain Input=0.3Vp-p, VVOL1/0= "00" 5.5 6 100kHz VVOL1/0= "01" 6.7 7.2 VVOL1/0= "10" 7.7 8.2 VVOL1/0= "11" 8.6 9.1 Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz. -0.3 Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz. -1.0 at 12MHz. -3 at 27MHz. -40 Group Delay Distortion At 4.43MHz with respect to 1MHz. Input Impedance Chrominance input (internally biased) 40 60 Input Signal f=100kHz, maximum with distortion < 1.0%, gain=6dB. Load Resistance (Note: 16) 150 Load Capacitance C1 (Note: 16) C2 (Note: 16) Dynamic Output Signal f=100kHz, maximum with distortion < 1.0% Y/C Crosstalk f=4.43MHz, 1Vp-p input. Among TVVOUT, -50 TVRC, VCRVOUT and VCRC outputs. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. 74 BW= 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. TBD chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. TBD chrominance &burst are 280mVpp, 4.43MHz. Note: 16. Refer the Figure 1.
R1 75 ohm Video Signal Output C2 max: 15pF C1 max: 400pF R2 75 ohm
max
6.5 6.5 7.7 8.7 9.6 0.3 0.5 -35 15 1.5 400 15 3 -
Units V V dB dB dB dB dB dB dB dB dB ns kohm Vpp ohm pF pF Vpp dB dB % Degree
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
Rev. 0.5 - 12 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
SWITCHING CHARACTERISTICS (Ta = 25C; VP=11.4 12.6V, VD = 4.75 5.25V, VVD1=VVD2 = 4.75 5.25V; CL = 20pF) Parameter Symbol Min typ fCLK 2.048 Master Clock Frequency 256fs: Duty Cycle dCLK 40 fCLK 3.072 384fs: Duty Cycle dCLK 40 fs 8 LRCK Frequency Duty Cycle Duty 45 Audio Interface Timing 312.5 tBCK BICK Period 100 tBCKL BICK Pulse Width Low 100 tBCKH Pulse Width High 50 tBLR BICK "" to LRCK Edge (Note: 17) 50 tLRB LRCK Edge to BICK "" (Note: 17) 50 tSDH SDTI Hold Time 50 tSDS SDTI Setup Time 2 Control Interface Timing (I C Bus): fSCL SCL Clock Frequency 1.3 tBUF Bus Free Time Between Transmissions 0.6 tHD:STA Start Condition Hold Time (prior to first clock pulse) 1.3 tLOW Clock Low Time 0.6 tHIGH Clock High Time 0.6 tSU:STA Setup Time for Repeated Start Condition 0 tHD:DAT SDA Hold Time from SCL Falling (Note: 18) 0.1 tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines 0.6 tSU:STO Setup Time for Stop Condition 0 tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width (Note: 19) tPD 150 Note: 17. BICK rising edge must not occur at the same time as LRCK edge. Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note: 19. The AK4704 should be reset by PDN= "L" upon power up. Note: 20. I2C is a registered trademark of Philips Semiconductors.
max 12.8 60 19.2 60 50 55
Units MHz % MHz % kHz % ns ns ns ns ns ns ns
400 0.3 0.3 50
kHz s s s s s s s s s s ns
ns
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.
Rev. 0.5 - 13 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Serial Interface Timing
Rev. 0.5 - 14 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
tPD
PDN
VIL
Power-down Timing
VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start
I2C Bus mode Timing
tSU:STO Stop
Rev. 0.5 - 15 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4704 should be reset once by bringing PDN pin = "L" upon power-up. The AK4704 has several operation modes. The PDN pin, AUTO bit, DAPD bit, MUTE bit and STBY bit control operation modes as shown in Table 1 and Table 2. Mode 0 1 2 3 4 5 6 7 PDN pin "L" "H" "H" "H" "H" "H" "H" "H" AUTO bit * 1 0 0 0 0 0 0 STBY bit * * 1 1 0 0 0 0 MUTE bit * * 1 0 1 1 0 0 DAPD bit * * * * 1 0 1 0 Mode Full Power-down Auto Startup mode (power-on default) Standby & mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down & Analog input) Normal operation (DAC operation) *: Don't Care
Table 1. Operation Mode Settings Register Control NOT available No video input Video input (***) Available Active Power down Active Power down Needed Not needed Needed (*): TVOUTL/R are muted by VMUTE bit in the default state. (**): Internally pulled down by 120kohm(typ) resister. (***): Video input to TVVIN or VCRVIN. (****): VCRC outputs 0V for termination. Table 2. Status of each operation modes Active (*) Active (****) Hi-Z/ Active Active Active MCLK, BICK, LRCK Not needed Audio Bias Level Power down Video Output Hi-Z TVFB, TVSB Hi-Z
Mode
VCRSB PullDown (**)
0 1
Full Power-down Auto Startup mode (power-on default)
2 3 4 5 6 7
Standby & mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down & Analog input) Normal operation (DAC operation)
Rev. 0.5 - 16 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Full Power-down Mode The AK4704 should be reset once by bringing PDN= "L" upon power-up.
PDN pin: Power down pin "H": Normal operation "L": Device power down.
Auto Startup Mode After when the PDN pin is set to "H", the AK4704 is in the auto startup mode. In this mode, all blocks except for the video detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN pin, the AK4704 goes to the stand-by mode automatically and sends "H" pulse via INT pin. To exit the auto startup mode, set the AUTO bit to "0".
AUTO bit (00H D3): Auto startup bit "1": Auto startup enable (default). "0": Auto startup disable (Manual startup).
DAC Power-down Mode The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit ="1", the zero-cross detection and offset calibration does not work.
DAPD bit (00H D2): DAC power-down bit. "1": DAC power-down. Analog-input mode. #39 pin: MCLK -> (NC) #40 pin: BICK -> DACR. Rch analog input. #41 pin: SDTI -> (NC) #42 pin: LRCK -> DACL. Lch analog input. "0": DAC operation. (default)
Standby Mode When the AUTO bit = MUTE bit = "0" and the STBY bit = "1", the AK4704 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values themselves are NOT changed by STBY bit = "1".
STBY bit (00H D0): Standby bit. "1": Standby mode. (default) "0": Normal operation.
Mute Mode (Bias-off Mode. 00H: D1) When the MUTE bit = "1", the bias voltage on the audio output goes to GND level. Bringing MUTE bit to "0" changes this bias voltage smoothly from GND to VP/2 by 2sec(typ.). This removes the huge click noise related the sudden change of bias voltage at power-on. The change of MUTE bit from "1" to "0" also makes smooth transient from VP/2 to GND by 2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off.
MUTE bit: Bias-off bit. "1": Set the audio bias to GND. (default) "0": Normal operation
Normal Operation Mode To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bit and STBY bit to "0". The DAC is in power-down mode until MCLK and LRCK are input. The AK4704 is in power-down mode until MCLK and LRCK are input. The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin.
Rev. 0.5 - 17 -
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Typical Operation Sequence (auto setup mode)
The Figure 2 shows an example of the system timing at auto setup mode.
PDN pin Clock, Data in TVVIN VCRVIN TVVOUT, VCRVOUT Audio out (DC)
Low Power Mode
Low Power Mode
Low Power Mode
don't care
don't care
No Signal
Signal in
No Signal
Signal in
No Signal
don't care
don't care
No Signal
Signal in
No Signal
don't care
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through) (GND)
Active (loop-through)
Figure 2. Typical operating sequence (auto setup mode)
Typical Operation Sequence (except auto setup mode)
The Figure 3 shows an example of the system timing at auto setup mode.
PDN pin AUTO bit MUTE bit STBY bit "1" (default) "1" (default) "1" (default) "0"
"Stand-by" "Mute" "Stand-by"
"0" "1" "0" "0" "1" "1"
Clock in Data in
D/A Out (internal)
don't care (2) don't care "0" GD
normal operation Audio data "0" GD (1)
don't care (2) don't care
(1)
TV-Source select
fixed to VCR in(Loop-through)
VCR in (default)
DAC
VCR in
(4)
offset calibration
TV out
VCR in
VCR in
(3)
Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode. (3) Mute the analog outputs externally if click noise(3) adversely affects the system. (4) In case of the CAL bit = "1", the offset calibration is always executed when the source of TVOUTL/R pins are switched to DAC after the STBY bit is changed to "0". To disable this function, set the CAL bit = "0". Figure 3. Typical operating sequence (except auto setup mode)
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2. Audio Block
System Clock
The external clocks required to operate the DAC section of AK4704 are MCLK, LRCK and BICK. The master clock (MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 3 illustrates corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC section of AK4704 is in the normal operating mode (STBY bit = "0" and DAPD bit = "0"). If these clocks are not provided, the AK4704 may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4704 should be reset by STBY bit = "0" after threse clocks are provided. If the external clocks are not present, place the AK4704 in power-down mode (STBY bit = "1"). After exiting reset at power-up etc., the AK4704 remains in power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz MCLK 256fs 384fs 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz Table 3. System clock example BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Audio Serial Interface Format (00H: D5-D4)
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial mode as shown in Table 4. In all modes, the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTI Format 16bit LSB Justified 18bit LSB Justified 24bit MSB Justified 24bit I2S Compatible BICK 32fs 36fs 48fs 48fs or 32fs Figure Figure 4 Figure 4 Figure 5 Figure 6 Default
Table 4. Audio Data Formats
LRCK BICK SDTI Mode 0 SDTI Mode 1
Don't care 15:MSB, 0:LSB Don't care 17:MSB, 0:LSB 17 16
15 14
0
Don't care
15 14
0
15
14
0
Don't care
17
16
15
14
0
Lch Data
Figure 4. Mode 0,1 Timing
Rch Data
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LRCK
BICK SDTI
23 22 23:MSB, 0:LSB
1
0
Don't care
23 22
1
0
Don't care
17
16
Lch Data
Figure 5. Mode 2 Timing
Rch Data
LRCK
BICK SDTI
23 22 23:MSB, 0:LSB
1
0
Don't care
23 22
1
0
Don't care
17
Lch Data
Figure 6. Mode 3 Timing
Rch Data
De-emphasis filter (00H: D7-D6)
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is controlled by the DEM0 and DEM1 bits. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 5. De-emphasis filter control
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Volume/Switch Control
The AK4704 has analog volume controls and switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in, Table 6, Table 8, Table 10 and Table 11 (Please refer to the block diagram in figure 1). (03H: D4-D3) DVOL1 0 0 1 1
DVOL0 0 1 0 1
Volume #0 Gain 0dB -6dB +2.44dB +4dB
Output Level 2Vrms (with 0dBFS input & volume #1=0dB.) 1Vrms (with 0dBFS input & volume #1=0dB.) 2.65Vrms (with 0dBFS input & volume #1=0dB.) 2Vrms (with -10dBFS input & volume #1=+6dB. Clips over -2.5dBFS digital input.)
Table 6. Volume #0 (at DAPD bit ="0". DAC mode) (03H: D4-D3) DVOL1 0 0 1 1
DVOL0 0 1 0 1
Volume #2 Gain +6dB 0dB (reserved) (reserved)
Output Level 2Vrms (with 1Vrms input & volume #1=0dB.) 1Vrms (with 1Vrms input & volume #1=0dB.) -
Table 7. Volume #2 (at DAPD bit ="1". analog input mode.) (02H: D5-D0) L5 L4 L3 L2 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 ... ... ... ... 0 0 0 0 0 0 0 0 Note: Do not exceed 3Vrms at analog output.
L1 1 0 0 1 ... 0 0
L0 0 1 0 1 ... 1 0
Gain +6dB +4dB +2dB 0dB (default) ... -60dB Mute
Table 8. Volume #1 (Analog Volume) (01H: D1-D0) TV1 TV0 0 0 0 1 1 0 1 1
Source of TVOUTL/R DAC VCRIN (default) Mute (Reserved)
Table 9. TVOUT Switch Configuration
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(01H: D2-D0) VOL TV1 TV0 Source of MONOOUT 0 0 0 DAC (L+R)/2 Bypass the 0 0 1 DAC (L+R)/2 volume #1 0 1 0 DAC (L+R)/2 0 1 1 (Reserved) 1 0 0 DAC (L+R)/2 Through the volume #1 1 0 1 VCRIN (L+R)/2 1 1 0 Mute 1 1 1 (Reserved) Table 10. MONOOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 0 0 0 1 1 0 1 1
Source of VCROUTL/R DAC TVIN (default) Mute Output of volume #1
Table 11. VCROUT Switch Configuration
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Zero-cross Detection and Offset Calibration
To minimize the click noise at changing the gain of volume #1, the AK4704 has a zero-cross detection and an offset calibration function. When DAPD bit ="1", the zero-cross detection and offset calibration does not work. 1. Zero-cross detection function (03H: D2-D0) When the ZERO bit = "1", the zero-cross detection function is enabled. The gain of volume #1 changes at the first zero-cross point from the acknowledgement of a volume changing command or when the zero-cross is not detected within the time set by ZTM1-0 bits (256/fs to 2048/fs). The zero-cross counter is initialized whenever a gain is issued. The zero-cross is detected on L/R channels independently. To disable this function, set the ZERO bit to "0". ZERO: Zero-cross detection enable for volume #1 0 : Disable. The volume value changes immediately without zero-cross. 1 : Enable (default). The volume value changes at a zero-crossing point or when timeout (ZTM1-0 bit setting) occurs. The internal comparator for zero-cross detection has a small offset. Therefore, the gain of volume #1 may change due to a zero-cross timeout before the comparator-based zero-cross detection occurs. When the new gain value 1EH(-2dB) is written while the gain of both Lch and Rch are 1FH(0dB), if the Lch detects the zero-cross prior to Rch, only the gain of Lch changes to 1EH(-2dB) while Rch waits for a zero-cross. After that, if the gain is set to 1DH(-4dB) before either a zero-cross or zero-cross timeout, the Rch keeps the same value and changes from 1FH to 1DH at next zero-cross or timeout.
WR[Gain=1EH] WR[Gain=1DH] Zero-cross
Gain Registers
1FH
1EH
1DH
Lch Gain
1FH
1EH
1DH
Rch Gain
1FH
1DH
Timer (256/fs to2048/fs) Timeout; (may have click noise)
zero-cross timer initialized
Figure 7. Zero-cross Operation (ZERO= "1") 2. Offset calibration function (03H: D5) Offset calibration is enabled when the CAL bit = "1". This function begins when the TVOUT source is switched to DAC after the STBY bit is changed to "0". It takes 1664/fs to execute the offset calibration cycle. During the offset calibration cycle, the analog outputs are muted. Once the offset calibration is executed, the calibration memory is held until PDN pin = "L" or the new calibration is executed. When the switch is changed from DAC to VCR during calibration, the calibration is discontinued, and resumed when TVOUT is switched back to DAC. If volume #1 gain is changed during calibration, the change takes place after calibration is complete.
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3. Video Block
Video Switch Control The AK4704 has switches for TV, VCR and RF modulator. Each switches can be controlled via registers independently. When AUTO bit = "1" or STBY bit = "1", these switch setting are ignored and set to fixed configuration (loop-through mode). Please refer the auto setup mode and standby mode.
(04H: D2-D0) Mode Shutdown Encoder CVBS /RGB Encoder Y/C 1 Encoder Y/C 2 VCR (default) TV CVBS (reserved) (reserved) VTV2-0 bit 000 001 010 011 100 101 110 111 Source of TVVOUT pin (Hi-Z) ENCV pin ENCV pin ENCY pin VCRVIN pin TVVIN pin Source of TVRC pin (Hi-Z) ENCRC pin ENCRC pin ENCC pin VCRRC pin (Hi-Z) Source of TVG pin (Hi-Z) ENCG pin Hi-Z Hi-Z VCRG pin (Hi-Z) Source of TVB pin (Hi-Z) ENCB pin (Hi-Z) (Hi-Z) VCRB pin (Hi-Z) (please refer notes)
Table 12. TV video output (04H: D5-D3) Mode Shutdown Encoder CVBS or Y/C 1 Encoder CVBS or Y/C 2 TV CVBS (default) VCR (reserved) (reserved) (reserved) VVCR2-0 bit 000 001 010 011 100 101 110 111 Source of VCRVOUT pin (Hi-Z) ENCV pin ENCY pin TVVIN pin VCRVIN pin Source of VCRC pin (Hi-Z) ENCRC pin ENCC pin (Hi-Z) VCRRC pin (please refer notes)
Table 13. VCR video output (04H: D7-D6) Source of RFV pin Encoder CVBS1 ENCV pin ENCG pin Encoder CVBS2 01 (Note: 22) VCR (default) 10 VCRVIN pin Shutdown 11 (Hi-Z) (when YC bit=0. please refer notes) Table 14. RF video output Mode Note: 21: When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively. Note: 22 When VTV2-0 bit ="001", TVG bit ="1" and VRF1-0 bit ="01", RFV pin output is same as TVG pin output (Encoder G). VRF1-0 bit 00
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Video Output Control (05H: D6-D0)
Each video outputs can be set to Hi-Z individually via control registers. These setting are ignored when the AUTO bit = "1". When the CIO bit = "1", the VCRC pin outputs 0V even if the VCRC bit = "0". When the CIO bit = "0", the VCRC pin follows the setting of VCRC bit. Please refer the "Red/Chroma Bi-directional Control for VCR SCART" TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB: TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control TVFB output control
0: Hi-Z (default) 1: Active.
Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The 4704 supports the bi-directional Red/Chroma signal on the VCR SCART.
(CIO bit & VCRC bit) 75 VCRC pin
#15 pin
VCRRC pin VCR SCART 0.1u
(AK4704)
Figure 8. Red/Chroma Bi-directional Control
CIO 0 0 1 1
VCRC State of VCRC pin 0 Hi-z (default) 1 Active 0 Connected to GND 1 Connected to GND Table 15 Red/Chroma Bi-directional Control
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RGB Video Gain Control (06H: D1-D0)
VVOL1-0 bits set the RGB video gain. VVOL1 0 0 1 1 VVOL0 0 1 0 1 Gain Output level (Typ. @Input=0.7Vpp) +6dB 1.4Vpp (default) +7.2dB 1.6Vpp +8.2dB 1.8Vpp +9.1dB 2.0Vpp Table 16. RGB video gain control
Clamp and DC-restore circuit control (06H: D6-D5, D3-D2)
Each CVBS and Y input has the sync tip clamp circuit. The sync tip voltage at each output is 0.7V(typ). This corresponds 0.35V(typ) at the SCART connector when matched by 75ohm resisters. The CLAMP1 and CLAMP0 bits select the input circuit for ENCRC pin (Encoder Red/Chroma) and VCRRC pin (VCR Red/Chroma) respectively. VCLP1-0 bits select the source of DC- restore circuit. CLAMP1 : Encoder Red/Chroma (ENCRC pin)input clamp control 0 : DC restore clamp active (for RED signal. default) 1 : Biased (for Chroma signal.) CLAMP0 : VCR R/C (VCRRC pin)input clamp control 0 : DC restore clamp active (for RED signal) 1 : Biased (for Chroma signal. default.) VCLP1-0 : DC restore source control VCLP1 0 0 1 1 VCLP0 Sync Source of DC Restore 0 ENCV (default) 1 ENCY 0 VCRVIN 1 (Reserved) When the AUTO bit = "1", the source is fixed to VCRVIN. Table 17. DC restore source control
Y/C Mixer for RF modulator (06H: D4)
When the YC bit = "1", the RFV pin outputs Y/C mixed signal from TVVOUT pin and TVRC pin. YC : Y/C mixing output control for RFV pin 0 : Follow VRF1-0 bits (default) 1 : Y/C mixing from TVVOUT and TVRC.
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4. Blanking Control
The AK4704 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0) FB1 0 0 1 1 TVFB pin Output Level 0V (default) 4V Same as VCR FB input (4V/0V) (Reserved) (note: minimum load is 150ohm) Table 18. TV Fast Blanking output FB0 0 1 0 1
SBT1-0: TV Slow Blanking output control (07H: D3-D2) SBT1 0 0 1 1 TVSB pin Output Level <2V (default) 5V<, <7V (Reserved) 10V< (note: minimum load is 10kohm) Table 19. TV Slow Blanking output SBT0 0 1 0 1
SBV1-0: VCR Slow Blanking output control (07H: D5-D4) SBV1 0 0 1 1 VCRSB pin Output Level <2V (default) 5V<, <7V (Reserved) 10V< (note: minimum load is 10kohm) Table 20. VCR Slow Blanking output SBV0 0 1 0 1
SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6) SBIO1 0 0 1 1 SBIO0 0 1 0 1 VCRSB pin Direction TVSB pin Direction Output Output (Controlled by SBV1,0) (Controlled by SBT1,0) (Reserved) (Reserved) Input Output (Stored in SVCR1,0) (Controlled by SBT1,0) Input Output (Stored in SVCR1,0) (Same output as VCR SB) Table 21. TV/VCR Slow Blanking I/O control
(default)
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5. Monitor Options and INT function
Monitor Options (08H: D3-D0)
The AK4704 has several monitors for the input DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins. SVCR1-0 bits, FVCR bit and VMON bit are reflected to these values. SVCR1-0: VCR Slow blanking status monitor SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 hold previous value. VCRSB pin input level SVCR1 SVCR0 < 2V 0 0 4.5 to 7V 0 1 (Reserved) 1 0 9.5< 1 1 Table 22. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". VCRFB pin input level FVCR <0.4V 0 1 V< 1 Table 23. VCR Fast Blanking monitor (Typical threshold is 0.7V) VMON : Video input monitor 0 : No video signal detected via TVVIN pin and VCRVIN pin. 1 : Detects video signal via TVVIN pin OR VCRVIN pin.
INT Function and Mask Options (09H: D3-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes "L" for 2usec(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resister. MVMON bit, MFVCR bit and MSVCR bit control the reflection of the status change of these monitors onto the INT pin from report to prevent to masks each monitor MVMON: Video input monitor mask. AUTO 0 0 1 1 MVMON 0 1 0 1 Reflection of the change of VMON bit to INT pin Reflect NOT reflect (e.g. masked) Reflect Reflect Table 24. Reflection of VMON change
(default)
MFVCR: FVCR Monitor mask. 0 : Change of MFVCR is reflected to INT pin. (default) 1 : Change of MFVCR is NOT reflected to INT pin. MSVCR: SVCR1-0 Monitor mask. 0 : Change of SVCR1-0 is reflected to INT pin. (default) 1 : Change of SVCR1-0 is NOT reflected to INT pin.
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6. Control Interface
I2C-bus Control Mode
1. WRITE Operations Figure 9 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 15). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0010001". If the slave address match that of the AK4704, the AK4704 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 16). A "1" for R/W bit indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4704. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 11). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 12). The AK4704 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 15). The AK4704 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4704 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 17) except for the START and the STOP condition.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W= "0"
SDA
S
Slave Address A C K
Sub Address(n)
Figure 9. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
Figure 10. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 11. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12. Byte structure after the second byte
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2. READ Operations Set R/W bit = "1" for READ operations. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4704 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-1. CURRENT ADDRESS READ The AK4704 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4704 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4704 discontinues transmission
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 13. CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address(R/W="0") and then the register address to read. After the register's address is acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4704 generates an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4704 discontinues transmission.
S T A R T R/W= "0" S T A R T S A C K Slave Address A C K R/W= "1" S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 14. RANDOM ADDRESS READ
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SDA
SCL S start condition P stop condition
Figure 15. START and STOP conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 16. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 17. Bit transfer on the I2C-bus
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Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Register Name Control Switch Main volume Zerocross Video switch Video output enable Video volume/clamp S/F Blanking control S/F Blanking monitor Monitor mask D7
DEM1 VMUTE 0 0 VRF1 CIO 0 SBIO1 0 0
D6
DEM0 0 0 VMONO VRF0 TVFB VCLP1 SBIO0 0 0
D5
DIF1 VCR1 L5 CAL VVCR2 VCRC VCLP0 SBV1 0 0
D4
DIF0 VCR0 L4 DVOL1 VVCR1 VCRV YC SBV0 0 0
D3
AUTO MONO L3 DVOL0 VVCR0 TVB CLAMP1 SBT1 VMON MVMON
D2
DAPD VOL L2 ZERO VTV2 TVG CLAMP0 SBT0 FVCR MFVCR
D1
MUTE TV1 L1 ZTM1 VTV1 TVR VVOL1 FB1 SVCR1 MSVCR
D0
STBY TV0 L0 ZTM0 VTV0 TVV VVOL0 FB0 SVCR0 0
When the PDN pin goes "L", the registers are initialized to their default values. While the PDN pin ="H", all registers can be accessed. Do not write any data to the register over 09H.
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Register Definitions
Addr 00H Register Name Control R/W default 0 1 1 1 D7 DEM1 D6 DEM0 D5 DIF1 D4 DIF0 R/W 1 0 1 1 D3 AUTO D2 DAPD D1 MUTE D0 STBY
STBY: Standby control 0 : Normal Operation 1 : Standby Mode(default). All registers are not initialized. DAC : powered down and timings are reset. Gain of Volume#1 : fixed to 0dB, Source of TVOUT : fixed to VCRIN, Source of VCROUT : fixed to TVIN, Source of MONOOUT : fixed to VCRIN, Source of TVVOUT : fixed to VCRVIN(or Hi-Z), Source of TVRC : fixed to VCRRC(or Hi-Z), Source of TVG : fixed to VCRG(or Hi-Z), Source of TVB : fixed to VCRB(or Hi-Z), Source of VCRVOUT : fixed to TVVIN(or Hi-Z), Source of VCRC : fixed to Hi-Z or VSS(controlled by CIO bit). MUTE: Audio output control 0 : Normal operation 1 : ALL Audio outputs to GND (default) DAPD: DAC power down control 0 : Normal operation (default). 1 : DAC power down. When DAPD bit = "1", the zero-cross detection and offset calibration does not work. AUTO: Auto startup bit 0 : Auto startup disable (Manual startup). 1 : Auto startup enable(default). Note: When the SBIO1bit = "1"(default= "0"), the change of AUTO bit may cause a "L" pulse on INT pin. DIF1-0: Audio data interface format control 00 : 16bit LSB Justified 01 : 18bit LSB Justified 10 : 24bit MSB Justified 11 : 24bit I2S Compatible (Default) DEM1-0: De-emphasis Response Control 00 : 44.1kHz 01 : off (Default) 10 : 48kHz 11 : 32kHz
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Addr 01H
Register Name Switch R/W default
D7 VMUTE 1
D6
0
D5 VCR1 0
D4 VCR0 1 R/W
D3
MONO
D2
VOL
D1 TV1 0
D0 TV0 1
0
0
1
TV1-0: TVOUTL/R pins source switch 00 : DAC 01 : VCRINL/R pins (Default) 10 : MUTE 11 : (Reserved) VOL: MONOOUT pin source switch 0 : Bypass the volume (fixed to DAC out) 1 : Through the volume (Default) MONO: Mono select for TVOUTL/R pins 0 : Stereo. (Default) 1 : Mono. (L+R)/2 VCR1-0: VCROUTL/R pins source switch 00 : DAC 01 : TVINL/R pins (Default) 10 : MUTE 11 : Volume #1 output VMUTE: Mute switch for volume #1 0 : Normal operation 1 : Mute the volume #1 (Default)
Addr 02H
Register Name Main volume R/W default
D7 0 0
D6 0 0
D5 L5 0
D4 L4 R/W 1
D3 L3 1
D2 L2 1
D1 L1 1
D0 L0 1
L5-0: Volume #1 control Those registers control both Lch and Rch of Volume #1. 111111 to 100011 : (Reserved) 100010 : Volume gain = +6dB 100001 : Volume gain = +4dB 100000 : Volume gain = +2dB 011111 : Volume gain = +0dB (default) 011110 : Volume gain = -2dB ... 000011 : Volume gain = -56dB 000010 : Volume gain = -58dB 000001 : Volume gain = -60dB 000000 : Volume gain = Mute
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[AK4704]
Addr 03H
Register Name Zerocross R/W default
D7 0 0
D6
VMONO
D5 CAL 1
D4 DVOL1 R/W 0
D3 DVOL0 0
D2 ZERO 1
D1 ZTM1 1
D0 ZTM0 1
0
ZTM1-0: The time length control of zero-cross timeout 00 : typ. 256/fs 01 : 512/fs 10 : 1024/fs 11 : 2048/fs (default) ZERO: Zero-cross detection enable for volume #1 control 0 : Disable The volume value changes immediately without zero-cross. 1 : Enable (default) The volume value changes when timeout or zero-cross before timeout. This function is disabled when STBY bit = "1". DVOL1-0: Volume #0/Volume #2 control. Please refer the Table 6 and Table 7 CAL: Offset calibration Enable 0 : Offset calibration disable. 1 : Offset calibration enable(default) VMONO: Mono select for VCROUTL/R pins 0 : Stereo. (Default) 1 : Mono. (L+R)/2
Rev. 0.5 - 35 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Addr 04H
Register Name Video switch R/W default
D7 VRF1 1
D6 VRF0 0
D5 VVCR2 0
D4 VVCR1 1 R/W
D3 VVCR0 1
D2 VTV2 1
D1 VTV1 0
D0 VTV0 0
VTV0-2: Selector for TV video output Please refer the Table 12. VVCR0-2: Selector for VCR video output Please refer the Table 13 RF0-1: Selector for RFV pin output (when YC bit=0). Please refer the Table 14. Addr 05H Register Name
output enable
D7
CIO
D6
TVFB 0
D5
VCRC
D4
VCRV
D3
TVB
D2
TVG
D1
TVR
D0
TVV
R/W default TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB: 0 1
R/W 0 0 0 0 0 0 0
TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control (please refer the Table 15) TVFB output control : Hi-Z (default) : Active.
When the CIO pin = "1", the VCRC pin is connected to GND even if VCRC= "0". When the CIO pin = "0", the VCRC pin follows the setting of VCRC bit. CIO: VCRC pin I/O control Please refer the Table 15.
Rev. 0.5 - 36 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Addr 06H
Register Name Video volume R/W default
D7
0
D6
VCLP1 0
D5
VCLP0
D4
YC
D3
CLAMP1
D2
CLAMP0
D1
VVOL1
D0
VVOL0
R/W 0 0 0 0 1 0 0
VVOL1-0: RGB video gain control 00: +6dB (default) 01: +7.2dB 10: +8.2dB 11: +9.1dB CLAMP1 : Encoder R/Chroma (ENCRC pin) input clamp control 0 : DC restore clamp active (for RED signal. default) 1 : Biased (for Chroma signal.) CLAMP0 : VCR R/C (VCRC pin) input clamp control 0 : DC restore clamp active (for RED signal) 1 : Biased (for Chroma signal. default.) YC : Y/C mixing output control for RFV pin 0 : Follow VRF1-0 bits (default) 1 : Y/C mixing from TVVOUT and TVRC. VCLP1-0 : DC restore source control 00: ENCV pin (default) 01: ENCY pin 10: VCRVIN pin 11: (Reserved) When the AUTO bit = "1", the source is fixed to VCRVIN pin. Addr 07H Register Name S/F Blanking R/W default D7 SBIO1 0 D6 SBIO0
0
D5 SBV1 0
D4 SBV0 R/W 0
D3 SBT1 0
D2 SBT0 0
D1 FB1 0
D0 FB0 0
FB1-0: TV Fast Blanking output control (for TVFB pin) 00: 0V (default) 01: 4V 10: follow VCR FB input (4V/0V) 11: (Reserved) SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kohm.) 00: <2V (default) 01: 5V<, <7V 10: (Reserved) 11: 10V< SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10kohm) 00: <2V (default) 01: 5V<, <7V 10: (Reserved) 11: 10V< SBIO1-0: TV/VCR Slow Blanking I/O control (please refer the Table 21)
Rev. 0.5 - 37 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Addr 08H
Register Name SB/FB monitor R/W default
D7 0 0
D6 0
0
D5 0 0
D4 0 0 READ
D3 VMON 0
D2 FVCR 0
D1 SVCR1 0
D0 SVCR0 0
SVCR1-0: VCR Slow blanking status monitor SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 hold previous value.
VCRSB pin input level SVCR1 SVCR0 < 2V 0 0 4.5 to 7V 0 1 (Reserved) 1 0 9.5< 1 1 Table 25. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". VCRFB pin input level FVCR <0.4V 0 1 V< 1 Table 26. VCR Fast Blanking monitor (Typical threshold is 0.7V) VMON : Video input monitor 0 : No video signal detected via TVVIN pin and VCRVIN pin. 1 : Detects video signal via TVVIN pin OR VCRVIN pin.
Addr 09H
Register Name Monitor mask R/W default
D7 0 0
D6 0
0
D5 0 0
D4 0 0
D3 MVMON R/W 1
D2 MFVCR 0
D1 MSVCR 0
D0 0 0
MVMON: Video input monitor mask. Please refer the Table 24. MFVCR: FVCR Monitor mask. 0 : The INT pin reflects the change of MFVCR bit. (default) 1 : The INT pin does not reflect the change of MFVCR bit. MSVCR: SVCR1-0 Monitor mask. 0 : The INT pin reflects the change of SVCR1-0 bit. (default) 1 : The INT pin does not reflect the change of SVCR1-0 bit.
Rev. 0.5 - 38 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
SYSTEM DESIGN
RFV MONOOUT
CVBS Audio MONO
RF Mod
Phono
TVOUTL TVOUTR TVRC TVG TVB TVFB TVVOUT CVBS/Y Y C Encoder R/C G/CVBS B ENCV ENCY ENCC ENCRC ENCGV ENCB VCRVIN MCLK MPEG Decoder BICK LRCK SDATA MCLK BICK LRCK SDTI SCK SDA PDN INT VCRRC VCRC VCRG VCRB VCRINL Micro Processor SCK SDA PDN Interrupt VCRINR VCRVOUT VCROUTL VCROUTR VCRSB TVVIN TVINL TVINR TVSB VCRFB
Audio L Audio R R/C G B Fast Blank Y/CVBS Y/CVBS Audio L Audio R Slow Blank TV SCART
Fast Blank Y/CVBS R/C
G B Audio L Audio R Y/CVBS Audio L Audio R Slow Blank VCR SCART
Figure 18. Typical Connection Diagram
Rev. 0.5 - 39 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be separated from system digital supply. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. The 0.1F ceramic capacitor should be placed as near to VD (VP, VVD1, VVD2) as possible.
Voltage Reference
Each DVCOM/PVCOM are signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current may be drawn from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to avoid unwanted coupling into the AK4704.
Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms (typ@VD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio pass band. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is 5.6V(typ.) for 000000H (@24bit). The DC voltage on analog outputs are eliminated by AC coupling.
FILT pin
The C (0.1 F) should be attached as shown in the Figure 19.
AK4704
FILT
C=0.1uF
VVSS
Figure 19. FILT pin
Rev. 0.5 - 40 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
External Circuit Example
Analog Audio Input pin
300ohm MONOIN TVINL/R VCRINL/R DACL/R
(Cable)
0.47F
Analog Audio Output pin
MONOOUT TVOUTL/R VCROUTL/R
10F
300ohm
(Cable)
Total > 4.5kohm
Analog Video Input pin
ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB
75ohm
(Cable) 75ohm
0.1F
Analog Video Output pin
TVVOUT, TVRC TVG, TVR, RFV VCRVOUT, VCRC 75ohm
(Cable) max 400pF 75ohm
max 15pF
Rev. 0.5 - 41 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
Slow Blanking pin
TVSB VCRSB 400ohm
(max 500ohm)
(Cable) max 3nF (with 400ohm) min: 10k ohm
Fast Blanking Input pin
VCRFB 75ohm (Cable) 75ohm
Fast Blanking Output pin
75ohm TVFB (Cable) 75ohm
Rev. 0.5 - 42 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 25 24 9.0 0.2
1.70Max 0.13 0.13 1.40 0.05
37
48 1 0.22 0.08 12
13
7.0
0.145 0.05 0.5 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
Rev. 0.5 - 43 -
2004/1
ASAHI KASEI
AKM CONFIDENTIAL
[AK4704]
MARKING
AK4704VQ XXXXXXX
1
XXXXXXXX: Date code identifier
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
Rev. 0.5 - 44 -
2004/1

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